1. Field of the Invention
The present invention relates to semiconductor dice and, more particularly, to a semiconductor die with heat and electrical pipes.
2. Description of the Related Art
Conventional semiconductor die have many advantages, but also suffer from a number of problem areas. One problem area is the removal of heat from the substrate of the die. The high current circuits of current-generation integrated circuits can generate significant amounts of heat in the substrate which, if not removed, can damage or erroneously bias adjacent circuits.
Another problem area is the surface area penalty that is paid to provide electrical contacts to the different regions of the substrate. For example, current-generation semiconductor die commonly have a large number of wells to support a large number of electrically-isolated CMOS circuits.
To place voltages on the wells, each well must be electrically contacted, and can be electrically contacted multiple times. Each electrical contact, in turn, consumes a region on the surface of the substrate (where the minimum size of the region is defined by the design rules of the fabrication process). Thus, a large number of well contacts consume a large amount of the surface area of the die.
FIG. 1 shows a cross-sectional diagram that illustrates a prior-art semiconductor die 100. As shown in FIG. 1, semiconductor die 100 includes a conventional semiconductor substrate 110 that has a top surface 110A, a bottom surface 110B, and a thickness T1 of approximately 500–750×10−6 m (500–750 microns or approximately 20–30 mils).
Further, die 100 includes a p− region 112 and a number of shallow trench isolation (STI) regions that are located in substrate 110. In addition, die 100 includes a p− well 114 and an n− well 116 that are located in substrate 110 to contact p− region 112. P− well 114 has a heavier dopant concentration than p− region 112 of substrate 110.
As further shown in FIG. 1, semiconductor die 100 includes a p+ substrate contact region 120 that is located in substrate 110 to contact p− region 112, a p+ well contact 122 that is located in substrate 110 to contact p− well 114, and an n+ well contact 124 that is located in substrate 110 to contact n− well 116.
Semiconductor die 100 additionally includes an NMOS transistor 126 and a PMOS transistor 128. NMOS transistor 126 has spaced-apart n+ source and drain regions 130 and 132 that are located in p− well 114, and a channel region 134 of p− well 114 that is located between source and drain regions 130 and 132. NMOS transistor 126 also has a gate oxide layer 136 that is formed on p− well 114 over channel region 134, and a gate 138 that is formed on gate oxide layer 136 over channel region 134.
PMOS transistor 128 has spaced-apart p+ source and drain regions 140 and 142 that are located in n− well 116, and a channel region 144 of n− well 116 that is located between source and drain regions 140 and 142. PMOS transistor 128 also has a gate oxide layer 146 that is formed on n− well 116 over channel region 144, and a gate 148 that is formed on gate oxide layer 146 over channel region 144.
As additionally shown in FIG. 1, die 100 includes a first dielectric layer 150 that is formed on top surface 110A of substrate 110 over p+regions 120, 122, 140, and 142, n+ regions 124, 130, and 132, and gates 138 and 148. Die 100 further includes a large number of contacts 152 that are formed through first dielectric layer 150 to make electrical connections with p+ regions 120, 122, 140, and 142, n+ regions 124, 130, and 132, and gates 138 and 148.
Semiconductor die 100 also includes a large number of metal-1 regions 156, such as traces and lines, that are formed on first dielectric layer 150 to make electrical connections with the contacts 152, and a second dielectric layer 160 that is formed on first dielectric layer 150 and the metal-1 regions 156.
Die 100 further includes a large number of vias 162 that are formed through second dielectric layer 160 to make electrical connections with the metal-1 regions 156, a large number of metal-2 regions 164, such as traces and lines, that are formed on second dielectric layer 160 to make electrical connections with the vias 162, and a top dielectric layer 170 that is formed on second dielectric layer 160 and the metal-2 regions 164.
In operation, significant amounts of heat can be generated in the channel regions 134 and 144 when transistors 126 and 128 are high current transistors, such as driver transistors. Further, as shown in FIG. 1, p+ regions 120 and 122 and n+region 124, along with the adjacent STI regions, consume a significant amount of the area of top surface 110A providing electrical connections to p− region 112 of substrate 110, p− well 114, and n− well 116, respectively.
As a result, there is a need for a semiconductor die that reduces the build up of heat in the high-current regions of the die. In addition, there is a need for a semiconductor die that reduces the amount of surface area that is consumed by the substrate and well contacts.